1. Field of the Invention
The present invention relates to a processor system, a processor and a method of arithmetic processing method capable of updating and debugging at least portion of a first program stored in a first program storage.
2. Related Background Art
A one chip micro computer ordinarily contains a mask ROM. Micro codes are embedded in such kind of mask ROM at manufactured time in advance. Since the mask ROM cannot rewrite data, if the micro codes include errors, the micro computer by itself has to be exchanged. Therefore, maintainability is not good, and it takes too much cost to revise the micro codes.
In order to overcome such a problem, a processor system in which when the micro codes in the program ROM include the errors, only the erroneous portions can be updated has been realized.
Such kind of conventional processor system has a program RAM in which the correct micro codes are stored, a ROM address register in which erroneous addresses of the micro codes in the program ROM are stored, a forced branch destination PC register in which addresses to be executed in the program RAM are stored, and an address comparator for determining whether or not a program counter coincides with erroneous addresses stored in the ROM address register. The processor system changes a value of the program counter into a value of the forced branch destination PC register. Therefore, correct micro codes stored in the program RAM are executed.
When the micro codes include a plurality of errors, however, the ROM address register and the forced branch destination PC register has to be provided by each erroneous location. Therefore, circuit size becomes large.
Although such kind of conventional processor system replaces the erroneous micro codes with correct micro codes, the system does not have a function for debugging the micro codes in the program ROM. Because of this, in order to perform the debug, a debug dedicated circuit has to be added to the processor system, thereby increasing the circuit size.